
Hsuan Yi Chou
18 years work experience in memory testing development engineering in the Semiconductor industry (ASX-51 Program coding/ New tester evaluation/... | Hsinchu City, Hsinchu City, Taiwan
*50 free lookup(s) per month.
No credit card required.
Hsuan Yi Chou’s Emails hs****@ev****.com
Hsuan Yi Chou’s Phone Numbers No phone number available.
Social Media
Hsuan Yi Chou’s Location Hsinchu City, Hsinchu City, Taiwan
Hsuan Yi Chou’s Expertise 18 years work experience in memory testing development engineering in the Semiconductor industry (ASX-51 Program coding/ New tester evaluation/ Testing Engineering/ P/C and Hifix wiring/ New product transition/ Application Support/ DDR4/LPDDR/DDR2/DDR3/QDR/ Async SRAM/SPI/MRAM). - Created new test program for mass production of new product. (high parallel, high speed,...etc.) - Fine tune test spec for yield gain. - New DRAM/SRAM family characteristic test program build up. - Reduce test time by new design for testing to save testing cost. - Provided technical and application support to reliability test. - Identified and developed a new KGD test program for DRAM/SRAM related products for Advantest T55xx and T53xx series. - Experienced with high speed (with TWIN-IO/DR) patterns build up. - Experienced with Verigy 93K tester for memory analysis
Hsuan Yi Chou’s Current Industry Everspin Technologies
Hsuan
Yi Chou’s Prior Industry
Winbond
|
Cypress Semiconductor
|
Everspin Technologies
Not the Hsuan Yi Chou you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Everspin Technologies
Taiwan Team Manager
Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Everspin Technologies
Staff Test Engineer
Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Cypress Semiconductor
Staff Testing Engineer
Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Winbond
Section Manager & Sr. Testing Engineer
Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)